The full report may not be provided due to having data that should not be released under an NDA. Diagrams Here
This project focuses on the collaborative design, implementation, and validation of a System-on-Chip (SoC) peripheral module integrating a USB Full-Speed Bulk-Transfer Endpoint with an AHB-Lite bus interface. The design is composed of three key modules: AHB-Lite Slave, USB RX and the USB TX. This has been implemented using a hardware description language (HDL) and synthesized at a target clock rate of 100 MHz. Performance metrics include synthesis frequency, area and timing analysis, and functional correctness validated through test benches. The results show trade-offs between module complexity, resource utilization, and performance, with the integrated design achieving robust USB bulk transfer functionality and performance with a reduction in CPU overhead by 62%.